1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to a multiple power source ESD protection circuit that operates through charge coupling.
2. Description of the Related Art
Failure of integrated circuit (IC) such as dynamic random access memory (DRAM) or static random access memory (SRAM) is often caused by electrostatic discharge during manufacturing or subsequent handling. For example, several hundred to several thousand volts can be generated when a person walks over a carpet, even if the surrounding relative humidity is high. When the relative humidity is low, more than ten thousand volts can be generated. If the electrified person touches a product chip, static electricity may suddenly discharge through the chip and result in chip failure. Hence, to prevent damages to silicon chip due to electrostatic discharge, various circuit protection methods are developed. The most common method of protecting against ESD is to install an on-chip ESD protection circuit between a bonding pad and connected internal circuit.
Since thickness of a gate oxide layer is reduced with an increase in the level of integration. the gate oxide layer will break down at the breakdown voltage at the source/drain junction or even lower. Under such circumstances, effectiveness of the original ESD protection circuit is greatly compromised. In addition, internal circuits are generally designed according to minimum design rules. The ESD protection circuit is not designed to withstand the large transient current produced in an electrostatic discharge (because sufficient separation must be allowed from a contact to the edge of the diffusion region and the gate region). Thus, high-level integrated circuits on a silicon chips are exceptionally vulnerable to electrostatic discharge. Consequently, ESD is one of the leading causes of failure in deep-submicron devices.
A conventional charge-coupled ESD protection circuit utilizes the coupled charges in an electrostatic discharge to increase the voltage in a floating gate and trigger the opening of a parasitic diode. Ultimately, the sudden current surge due to ESD is channeled away and the internal circuit inside the silicon chip is protected. However, due to the presence of a parasitic diode, effectiveness of the positive voltage stress to ground line Vss and the negative voltage stress to voltage source Vdd type of conventional charge-coupled ESD protection circuit is diminished.
FIG. 1 is a schematic diagram of a conventional ESD charge-coupled protection circuit. As shown in FIG. 1, the ESD charge-coupled protection circuit 10 is installed between a bonding pad 12 and an internal circuit 14. The protection circuit 10 includes two N-type metal-oxide-semiconductor (NMOS) transistors 16 and 18 and two P-type metal-oxide-semiconductor (PMOS) transistors 20 and 22. The source terminal of the NMOS transistor 16 is grounded (via a ground line Vss); the gate terminal is connected to the drain terminal of the NMOS transistor 18; and the source terminal is connected to the bonding pad 12. The source terminal of the NMOS transistor 18 is connected to the ground line Vss and the gate terminal is connected to a voltage source Vdd. The source terminal of the PMOS transistor 20 is connected to the voltage source Vdd; the gate terminal is connected to the drain terminal of the PMOS transistor 22; and the drain terminal is connected to the bonding pad 12. The source terminal of the PMOS transistor 22 is connected to the voltage source Vdd and the gate terminal is connected to the ground line Vss.
In normal operation, the gate terminal of the NMOS transistor 18 and the gate terminal of the PMOS transistor 22 are connected to the voltage source Vdd and the ground line Vss, respectively. Hence, both transistors 18 and 22 are turned on. The gate of the NMOS transistor 16 and the gate of the PMOS transistor 20 are in a non-floating state. Hence, both transistors 16 and 20 are turned off. Under such circumstances, there is no charge coupling.
When there is electrostatic discharge (ESD), using a positive stress as an example, since the voltage source Vdd is in a floating state (an abnormal operating condition), the NMOS transistor 18 is turned off. Within a very short time, the gate terminal is in a floating state. Hence, the positive stress voltage applied to the bonding pad 12 couples with the gate terminal of the NMOS transistor 16 through a parasitic capacitor 24 between the drain and the gate terminal of the NMOS transistor 16. The coupling of the parasitic capacitor 24 triggers the NMOS transistor 16 so that the positive stress voltage is discharged through a ground line Vss via the NMOS transistor 16.
Due to the forward bias of the parasitic diode 26 of the PMOS transistor 20, a positive stress voltage applied to the bonding pad 12 is fed back to the gate terminal of the NMOS transistor 18 via the parasitic diode 26 and the voltage source Vdd. Hence, the NMOS transistor 18 is turned on. Therefore, the degree of charge coupling decreases and the capacity for ESD protection deteriorates. Similarly, a negative stress voltage applied to the bonding pad 12 is fed back to the voltage source Vdd.